Pages

April 16, 2011

Logic Gates



          Various forms of logical building blocks are available in integrated circuit form. These logical building blocks are called “gates,” with each gate having a distinct function. Logic gates can be further combined into more complex digital building blocks to perform a variety of counting, memory, and timing functions. 
          Digital ICs are grouped into families, with each family possessing certain desirable traits that make them more or less suited to a variety of applications. One logic family might not be compatible with another family, so it is typical for the designer to use only one family type for each application. The most commonly used logic families in the present market are complementary metal oxide silicon (CMOS) and transistor-transistor logic (TTL). 
          Logic gates respond to “high” or “low” voltage levels. The specific voltage level for a “high” or “low” condition will vary from one logic family to another. For example, a logical one (high) in TTL logic is about 5 volts; in contrast, a possible 12-volt level might be used for CMOS logic. However, the functional operation and symbolic representation is universal throughout all of the families. In figure below lists some of the more common logic devices and their associated symbols. 




          Logic gates, and other logic devices, are functionally defined by using truth tables. The second figure illustrates a variety of truth tables for some common logic gates. Compare the AND-gate illustration in first figure with its corresponding truth table in second figure. Because the AND gate has two input leads, there are a total of four possible logic conditions that could occur on the inputs. Notice that the truth table lists the four possible input conditions; together with each of their resultant outputs for each condition. As shown by the truth table, the only time that the output goes “high” is when the A input “and” the B input are high. 
          Logic gates can have more than two inputs. Second figure illustrates the truth table for a three-input AND gate. Common logic gates are available with up to eight inputs. 
Referring again to first figure, note the OR gate and its associated truth table in second figure. As the name implies, its output goes high whenever a high appears on the A input, or on the B input (or both). 
In digital terminology, a not function means that a logical condition is inverted, or reversed. A NAND gate (short for not AND) is an AND gate, with the output inverted. Notice that the outputs in the truth tables for the AND gate, and the NAND gate, are simply inverted. This same principle holds true for the OR and NOR gates. 
          It is common for the output of one logic gate to provide inputs for several other logic gates. The maximum number of inputs that can be driven by a particular logic gate is specified as its fanout. Typical logic gates have fanouts ranging from 5 to 20. If it becomes necessary to drive a greater number of inputs than the fanout of a particular gate, a buffer is used to increase the fanout capability. The symbol for a buffer is illustrated in first figure. 
          The need often arises to invert a logic signal. The symbol for an inverter is shown in first figure. An inverter is sometimes called a not gate. Note that it has a small circle on its output just like the NOT AND (NAND) and NOT OR (NOR) gates. Anytime a small circle appears on an input or output of a logic device, it is symbolizing the inversion of the logic signals (or data). Also notice the horizontal line above the A output of the inverter. It is called a not symbol. Whenever a horizontal line is placed above a logic expression, it means that it is inverted. 
          Another common type of logic gate is the exclusive OR gate. Refer to its symbol and the associated truth table in first and second figures. As the truth table indicates, its output only goes high when its inputs are different from each other. The exclusive NOR gate provides the same logic function with an inverted output.




No comments:

Post a Comment